Since the electrical industry has changed with each passing day, the CPU and chipset are advancing constantly, such that the transmission speed of the PCI interface is the choke point or bottle neck for the ultimate speed of the computer system. Now the high-speed PCI (PCI Express) is presented, having more advantages such as high-performance, enhanced bandwidth, advanced power management function, hot swap/plug, point to point transmission and serial connection, which are desired by users such that manufacturers develop related electronic products with the high-speed PCI interface. However, since the software and hardware of the computer system are powerful and high-speed, the stable operation thereof is important to the user, such that every manufacturer strives toward these goals.
Usually, while the user is operating the computer, the computer may crash, for example: the high-speed PCI device falls into an endless loop or becomes unable to be awakened from Suspend to RAM (STR) of the hibernate mode. Now, if the computer system adopts a high-speed PCI device with PCI Express interface, which sends a hot reset packet to the out-of-control high-speed PCI device for constructing a normal coupling with the computer system.
Referring to FIG. 1, it is shown that the electrical connections diagram of the system with high-speed PCI interface of the prior art. As shown in the figure, the system 10 comprises a north bridge 11 with at least one root port 111, at least one high-speed PCI device 13 and a south bridge 15. When the power is engaged, the south bridge 15 can transmit a PCI resetting signal (PCI RST#) to a buffer 112 through a PCI reset signal line 151, and then the buffer 112 can transmit the PCI resetting signal to the high-speed PCI device 13 through a reset signal line 113 such that the system 10 will proceed with an initializing action for the high-speed PCI device 13. After the system 10 is finished with the initializing action, the user can operate the system 10 normally. When the high-speed PCI device 13 fails to communicate with the north bridge 11 normally, the system 10 will adopt the root port 111 for transmitting a hot reset packet to the high-speed PCI device 13 through a high-speed PCI bus 117, such that the high-speed PCI device 13 will proceed with the initializing action to communicate normally with the north bridge 11 again. However, the high-speed PCI device 13 may not be able to execute the hot reset packet, the only way to reset the high-speed PCI device 13 is to turn off and then turn on the power again. In other words, this will cost a lot of time of the user to do so.